NASA's High Performance Spaceflight Computing (HPSC) project has advanced to testing phase with a new radiation-hardened system-on-a-chip (SoC) designed to deliver transformative gains in onboard spacecraft computing. Developed in partnership with Microchip Technology Inc., the processor is undergoing rigorous evaluation at NASA’s Jet Propulsion Laboratory (JPL) in Southern California to validate its resilience and performance under spaceflight conditions.
Overview
The HPSC processor represents a major leap from current spaceflight computing hardware, which relies on decades-old, radiation-tolerant chips with limited processing power. These legacy systems prioritize reliability over performance, constraining capabilities such as real-time data analysis, autonomous decision-making, and high-bandwidth science operations. The new SoC aims to overcome these limitations by integrating modern multicore architecture with fault tolerance and radiation hardening.
Built by Microchip Technology Inc. of Chandler, Arizona, the processor was selected by JPL in 2022 under a commercial partnership in which the company funded its own research and development. The chip is part of NASA’s Game Changing Development (GCD) program, managed by the Space Technology Mission Directorate at NASA Langley Research Center in Hampton, Virginia.
What it does
The HPSC SoC integrates central processing units, computational offloads, advanced networking, memory, and input/output interfaces into a single compact, energy-efficient package. As a radiation-hardened system, it is engineered to endure extreme temperature swings, electromagnetic interference, and high-energy particle impacts from solar and cosmic radiation—conditions that can trigger system faults or force spacecraft into safe mode.
Testing at JPL, which began in February, includes radiation, thermal, shock, and functional performance evaluations. Engineers are running high-fidelity simulations of real NASA landing scenarios that demand intensive processing of sensor data—tasks previously requiring bulky, power-hungry hardware. Early results indicate the processor is operating at 500 times the performance of current radiation-hardened spaceflight computers.
The chip’s performance leap enables advanced capabilities:
- Real-time artificial intelligence for autonomous navigation and hazard detection
- Onboard scientific data analysis to prioritize downlink content
- Faster processing for deep space missions with limited Earth contact
- Support for crewed habitats on the Moon and Mars through responsive computing systems
Samples have been distributed to early access partners in defense and commercial aerospace. Once certified, the processor will be integrated into future NASA missions, including Earth orbiters, planetary rovers, and deep-space probes.
Tradeoffs
While the performance increase is substantial, the design prioritizes reliability and radiation tolerance over raw speed. The use of radiation-hardened fabrication limits how closely the chip can follow commercial semiconductor scaling trends. However, its modular, flexible architecture allows for software-defined reconfiguration during missions, balancing performance with mission-critical fault tolerance.
When to use it
The HPSC SoC is intended for missions requiring long-duration reliability in high-radiation environments, such as interplanetary travel, lunar surface operations, and extended Earth orbit. It is not suited for low-cost, short-duration platforms like small satellites where commercial off-the-shelf components remain more practical.
Microchip also plans to adapt the technology for terrestrial applications in aviation and automotive manufacturing, where reliability under extreme conditions is critical.
Bottom line
The HPSC processor marks a pivotal shift in spaceflight computing, enabling smarter, more autonomous missions. With testing yielding strong early results, the chip could become the standard for NASA and aerospace partners within this decade.